This summer i am working with Dr Kota Solomon Raju, Senior Scientist at CEERI, Pilani and my classmate Kunal Kedar on FPGA board design. The aim would be develop a complete understanding of what is required to make a stand alone FPGA system , which can be further used to some application which needs custom peripherals to be interfaced.
We are going to design it for Virtex 5 series . We are currently looking at only 2 packages FF1136 and FF1760. We will be using a Virtex 5 AFX FF1136 Proto board to test the design .
The first task was to understand the pins of the FPGA. Unlike other Integrated circuits , all the data about the FPGA cannot be put into one document . So Xilinx provide different documents addressing different users and aspects . The pin information document is what we are looking at. First we have created a simplified layout of pins considering the similarities of the io banks. It cannot be understood in a single , one needs to do two to three iteration to draw a optimal and meaningful pinout .
We are going to design it for Virtex 5 series . We are currently looking at only 2 packages FF1136 and FF1760. We will be using a Virtex 5 AFX FF1136 Proto board to test the design .
The first task was to understand the pins of the FPGA. Unlike other Integrated circuits , all the data about the FPGA cannot be put into one document . So Xilinx provide different documents addressing different users and aspects . The pin information document is what we are looking at. First we have created a simplified layout of pins considering the similarities of the io banks. It cannot be understood in a single , one needs to do two to three iteration to draw a optimal and meaningful pinout .
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